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| Recent Parallel Processing White Papers, Webcasts and Case Studies - ZDNet |
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| Aerospace Firm Attracts Customers With High-Performance Computing |
(Wed, 18 Jun 2008)
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| Washington-based Andrews Space is an affordable integrator of aerospace systems and a developer of advanced space technologies. Andrews Space needed a new parallel-processing computing environment with the high-performance that complex contracts demand, and the cost-effectiveness to meet its budget requirements. After researching processors and interconnect technology, Andrews Space elected to create its new parallel-processing computing cluster by linking Dell servers through a Cisco SFS 7000P InfiniBand Server Switch. |
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| OpenMP and Automatic Parallelization in GCC |
(Thu, 12 Jun 2008)
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| This paper describes the design and implementation of the OpenMP specification v2.5 in GCC. The implementation supports all the languages specified in the standard (C, C++ and Fortran), and it is generally available on any platform that supports POSIX threads. Emphasis is placed on the internal architecture and, in particular, the intermediate representation, which could be used in the implementation of automatic parallelization techniques. The paper also presents performance results on the SPEC OMP2001 benchmark. |
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| Developing a Business-Driven Strategy for Natural Language Processing Technologies |
(Wed, 11 Jun 2008)
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| Through On Demand Innovation Services - a partnership between IBM Research and Global Business Services - IBM was able to give the insurance and banking executives an integrated view of the technology itself and potential business applications. As a leader in the fields of speech and language processing, IBM Research was well-positioned to provide a comprehensive overview of NLP and its capabilities. Global Business Services (GBS) employed its Capability Maturity Model technique to help the company's decision makers understand the full range of NLP possibilities and implications for their business. The process gave the client both the big picture and the in-depth information it needed to forge a strategic pathway toward market leadership. |
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| Intel Threading Tools and OpenMP |
(Fri, 30 May 2008)
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| Explicit threading methods, such as Windows threads or POSIX threads, use library calls to create, manage, and synchronize threads. Use of explicit threads requires an almost complete restructuring of affected code. On the other hand, OpenMP is a set of pragmas, API functions, and environment variables that enable one to incorporate threads into the applications at a relatively high level. The OpenMP pragmas are used to denote regions in the code that can be run concurrently. An OpenMP-compliant compiler transforms the code and inserts the proper function calls to execute these regions in parallel. In most cases, the serial logic of the original code can be preserved and is easily recovered by ignoring the OpenMP pragmas at compilation time. |
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| Extending OpenMP to Clusters |
(Fri, 30 May 2008)
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| OpenMP is a well-known parallel programming paradigm for shared-memory multiprocessors. In the past, OpenMP has been confined to Symmetric Multi-Processing (SMP) machines and teamed with Message Passing Interface (MPI) technology to make use of multiple SMP systems. A new system, Cluster OpenMP, is an implementation of OpenMP that can make use of multiple SMP machines without resorting to MPI. This advance has the advantage of eliminating the need to write explicit messaging code, as well as not mixing programming paradigms. The shared memory in Cluster OpenMP is maintained across all machines through a distributed shared-memory subsystem. Cluster OpenMP is based on the relaxed memory consistency of OpenMP, allowing shared variables to be made consistent only when absolutely necessary. |
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| Threading Applications With the Intel Compiler 10.0 Professional Editions |
(Fri, 30 May 2008)
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| Once the decision to thread an application is made, judiciously choosing the right implementation and the right tools can make a big difference to the efficiency of the development process. The Intel Compiler 10.0 Professional Editions contain all of the tools the user needs to express the parallelism in your applications. The Intel compilers support OpenMP and native OS threads. The Professional Editions also include Intel Threading Building Blocks and the threaded implementation of Intel Integrated Performance Primitives and Intel Math Kernel Library. Together, these software products provide a rich set of tools and technologies to thread applications and take advantage of multi-core platforms. |
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| Managing Large Data With SAS SPD Server |
(Fri, 30 May 2008)
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| This paper provides the concepts behind demonstrations of how one can enhance query performance when one uses the SAS SPD Server to manage large data tables. This paper does not cover the main concepts for Dynamic Clusters or Parallel Join. This paper focuses on managing data within standard SAS Scalable Performance Data Server (SPD Server) tables, and therefore Dynamic Cluster tables, to enhance data querying. There are three common types of queries for which data within a table can be optimized: ordered processing, subsetting, and a hybrid of ordered processing and subsetting. |
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| Patterns for Parallel Processing of Non-Linear Hierarchical Structures |
(Wed, 19 Mar 2008)
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| Processing of large non-linear hierarchical structures could achieve better performance whether implemented over parallel environments. Although there are a wide range of applications for such parallelized structures, it lacks well-defined design patterns to model them, even though some parallel programming patterns had already been proposed. This paper proposes a set of design patterns that address these issues as well as it suggests some applications of them. |
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| Total Power-Optimal Pipelining and Parallel Processing Under Process Variations in Nanometer Technology |
(Wed, 19 Mar 2008)
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| This paper explores the effectiveness of the simultaneous application of pipelining and parallel processing as a total power (static plus dynamic) reduction technique in digital systems. Previous studies have been limited to either pipelining or parallel processing, but both techniques can be used together to reduce supply voltage at a fixed throughput point. According to the first-order analyses, there exist optimal combinations of pipelining depth and parallel processing width to minimize total power consumption. The paper shows that the leakage power from both subthreshold and gate-oxide tunneling plays a significant role in determining the optimal combination of pipelining depth and parallel processing width. |
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| Distributed and Parallel Database Systems |
(Wed, 19 Mar 2008)
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| The maturation of Database Management System (DBMS) technology has coincided with significant developments in distributed computing and parallel processing technologies. The end result is the emergence of distributed database management systems and parallel database management systems. These systems have started to become the dominant data management tools for highly data-intensive applications. The integration of workstations in a distributed environment enables a more efficient function distribution in which application programs run on workstations, called application servers, while database functions are handled by dedicated computers, called database servers. This has led to the present trend in distributed system architecture, where sites are organized as specialized servers rather than as general-purpose computers. |
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| Intelligent Perceptual Information Parallel Processing System Controlled by Mathematical AIM Model |
(Wed, 19 Mar 2008)
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| This paper studies an intelligent perceptual information processing system in which plural processing can run in parallel. The proposed mathematical Activation-Input-Modulation (AIM) model controls each execution frequency of plural processing independently based on degrees of stimuli detected by external sensors. When external stimuli are detected by some of external sensors, information processing tasks related to the sensors have a priority to be executed, and the stimuli are stored in a memory system. When no external stimulus is detected, the execution frequencies of almost external information processing decrease, and information stored in the memory system is organized by internal information processors. |
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| Optimizing Parallel Itineraries for KNN Query Processing in Wireless Sensor Networks |
(Wed, 19 Mar 2008)
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| Spatial queries for extracting data from wireless sensor net-works are important for many applications, such as environmental monitoring and military surveillance. One such query is K Nearest Neighbor (KNN) query that facilitates sampling of monitored sensor data in correspondence with a given query location. Recently, itinerary-based KNN query processing techniques, that propagate queries and collect data along a pre-determined itinerary, have been developed concurrently. These research works demonstrate that itinerary-based KNN query processing algorithms are able to achieve better energy efficiency than other existing algorithms. However, how to derive itineraries based on different performance requirements remains a challenging problem. |
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| Parallel Distributed Processing and Lexical - Semantic Effects in Visual Word Recognition: Are a Few Stages Necessary? |
(Wed, 19 Mar 2008)
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| D. C. Plaut and J. R. Booth (2000) presented a parallel distributed processing model that purports to simulate human lexical decision performance. This model (and D. C. Plaut, 1995) offers a single mechanism account of the pattern of factor effects on Reaction Time (RT) between semantic priming, word frequency, and stimulus quality without requiring a stages-of-processing account of additive effects. Three problems are discussed. First, no evidence is provided that this model can discriminate between words and nonwords with the same orthographic structure and still produce the pattern of factor effects on RT it currently claims to produce. |
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| Adaptive Sensing and Image Processing With a General-Purpose Pixel-Parallel Sensor/Processor Array Integrated Circuit |
(Wed, 19 Mar 2008)
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| In this paper, a pixel-parallel image sensor/processor architecture with a fine-grain massively parallel SIMD analogue processor array is overviewed and the latest VLSI implementation, SCAMP-3 vision chip, comprising 128 × 128 array, fabricated in a 0.35µm CMOS technology, is presented. Examples of real-time image-processing executed on the chip are shown. Sensor-level data reduction, wide dynamic range and adaptive sensing algorithms, enabled by the sensor-processor integration, are discussed. |
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| Implementation of Parallel Algorithm "Conveyer Processing" for Images Processing by Filter 'Mean' |
(Wed, 19 Mar 2008)
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| This paper implements a parallel algorithm for recursive image processing by filter 'Mean'. For implementation of parallel program is used MPI (Message Passing Interface) library. It is shown execution of a program with one and more processors. The program works with 24-bit BMP images. It is made a comparison between sequential and parallel "Conveyer processing" algorithms. |
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